Cadence® Denali® DDR Memory IP is a family of system-level IP solutions consisting of memory controller and memory PHY IP. Our DDR IP offering addresses a broad range of high-performance and low-power requirements for today’s ever-changing environment.

We offer DDR controller and PHY IP that supports all widely used DDR protocols, including LPDDR4, LPDDR3, LPDDR2, DDR4, DDR3, and DDR3L. The DDR Controller IP is extremely flexible and can be configured to support almost any application. Two DDR PHY architectures, high-speed (HS) PHY and low-power (LP) PHY, are designed to provide you with configurable solutions that meet the specific needs of your system and application.

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  • Lowest-latency DDR controller and PHY IP
  • Extremely flexible in configuration and PHY placement with Firm PHY model
  • Advanced DDR PHY clocking architecture minimizes clock jitter

DDR Resource Page

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Learn more about how Cadence provides a one-stop shop for all your LPDDR4 needs


DDR ControllersFully configurable and customizable DDR controllers

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DDR Firm PHYConfigurable width DDR PHY's

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DDR Hard PHYFully hardened DDR PHY's

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Multi-Protocol DDR IPIntegrates a LPDDR4/3 DDR4/3 controller and a LPDDR4/3 DDR4/3 Firm PHY

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