Cadence® Denali® DDR Memory IP is a family of system-level IP solutions consisting of memory controller and memory PHY IP. Our DDR family of IP addresses a broad range of high-performance as well as low-power requirements for today’s ever-changing environment.

Our DDR memory IP supports all DDR specifications and includes DDR controllers that provide unsurpassed flexibility with the ability to configure and customize a controller to your specific needs. It provides the added value of multi-standard DDR support in a single IP core. For example, we can provide a controller IP that supports DDR4, DDR3, DDR3L, LPDDR3, and LPDDR2 as a single IP solution.

Our DDR PHY IP family includes two families of DDR PHYs, high-speed (HS) PHYs and low-power (LP) PHYs, to address a range of applications for DDR. Delivery options include Firm IP and Hard IP, providing flexibility either to integrate a customized memory interface in your design, or to utilize a standard implementation to speed up integration on a wide range of technology nodes, including advanced nodes, such as 16nm FinFET.


DDR Resource Page

Click here for more information on our DDR4 16nm FinFET IP


DDR Controllers Fully configurable and customizable DDR controllers

Cadence IP provides you with an open IP platform and IP Factory approach that delivers fully configurable/customizable DDR controller IP to fit your specific requirements. Cadence Denali DDR Controller IP supports all current DDR specifications: DDR4, DDR3, DDR2, DDR, LPDDR3, LPDDR2, LPDDR, and the upcoming LPDDR4 specification.

Our DDR controller IP can be customized to support a single protocol, or integrated to support a combination of different DDR protocols, features, and functions. With Cadence, you have the freedom to determine the DDR protocols supported, the bitwidth needed, the PHY interface (DFI 4.0, DFI 3.1, DFI 3.0, DFI 2.1, DFI 2.0, or DFI 1.0), and the local bus interface (AHB™, OCP, DEN, AXI3, AXI4); and to select optimized functions (low power modes, DFI LPI modes, BIST, ECC, or DIMM). Our DDR controller IP also supports multiple clients and includes an arbitration block with priority engine to maximize memory system throughput.


DDR Controller IP DDR4, DDR3, DDR3L, DDR2, DDR

DDR Firm PHY Configurable width DDR PHY's

Cadence Firm PHY IP offers our most flexible solution for your memory PHY design. Using our proven PHY with hard Data slice, CA slice, address and control logic, I/O and decap cells, phase-locked loop (PLL), and glue logic, you can quickly create a full-featured PHY that meets your most demanding requirements.

Each Firm PHY IP includes a hard 8-bit data slice that converts data read and write signals to and from the controller interface (DFI) into data read and write signals required by the particular memory interface being developed. The hard data slice in Firm PHY IP can be duplicated as many times as necessary for your memory interface data width.

Each Firm PHY IP also includes a command/address slice for conversion of control, command and address signals in a way similar to the data slice, which can also be duplicated per protocol and address width needs. The availability of CA slice is speed and protocol dependent.


High-Speed PHY IP

High-Speed Firm PHY's

Low-Power PHY IP

Low-Power Firm PHY's

DDR Hard PHY Fully hardened DDR PHY's

Cadence Hard PHY IP provides silicon-proven solutions that are ready to use. Our DDR Hard PHY IP can be implemented in a variety of DDR configurations, speeds and bit widths offered in various process nodes, and geometries. With Cadence IP, you can achieve first-silicon success in your system-on-chip (SoC) development in the shortest amount of time with the lowest amount of risk.

Consult with Cadence and choose from two families of Hard PHY IP, high speed (HS) and low power (LP), to address a range of applications with the optimal PHY IP suited to your needs.


Cadence Hard PHY IP offering includes all process nodes, protocol and speed combinations listed in the DDR Firm PHY products tables. For any combination not listed, please contact your local sales representative for availability.



Multi-Protocol DDR IP Integrates a LPDDR4/3 DDR4/3 controller and a LPDDR4/3 DDR4/3 Firm PHY

Cadence multiprotocol DDR IP integrates a LPDDR4/3 DDR4/3 controller and a LPDDR4/3 DDR4/3 Firm PHY, capable of speeds up to 3200Mbps, into a single, fully verified subsystem IP. The multiprotocol DDR IP offering supports both high-performance PC DRAM standards, DDR4 and DDR3, as well as the most advanced low-power DRAM standards, LPDDR4 and LPDDR3, and meets the requirements of many advanced applications from low-power mobile to high-performance, reliability sensitive infrastructure.

Cadence multiprotocol DDR IP solution also meets the emerging demands of high performance consumer applications by providing the alternative of higher performance LPDDR4 option to an application that has traditionally only used PC DRAM.  This solution enables system designers to take advantage of the highest performance DRAMs with options to manage bill of material (BOM) costs by taking advantage of market driven DRAM pricing. There is an evolutionary change in the DRAM market that, in the future, will drive the cost of low power DRAM devices to be cost effective enough to use in non-mobile consumer products such as Set-top box, HDTV, printers, etc.

Cadence also offers, as stand-alone products, the LPDDR4/3/DDR4/3 Controller IP and LPDDR4/3/DDR4/3 Firm PHY IP.

 Key Features

  •  Supports any combination of LPDDR4/3/DDR4/3
  •  Highly configurable multiport memory controller
    • Multiple configurable ports
    • ECC, CRC, parity etc.
    • BIST
    • Configurable arbitration options
  • Features rich Multi-protocol PHY
    • Perbit deskew
    • Loop back test
    • Per rank leveling


Integrated LPDDR4/3 and DDR4/3 Controller and Firm PHY up to 3200 Mbps
LPDDR4/3/DDR4/3 Controller up to 3200 Mbps
LPDDR4/3/DDR4/3 Firm PHY up to 3200 Mbps