DDR IP

Cadence® Denali® DDR Memory IP is a family of system-level IP solutions consisting of memory controller and memory PHY IP. Our DDR family of IP addresses a broad range of high-performance as well as low-power requirements for today’s ever-changing environment.

Our DDR memory IP supports all DDR specifications and includes DDR controllers that provide unsurpassed flexibility with the ability to configure and customize a controller to your specific needs. It provides the added value of multi-standard DDR support in a single IP core. For example, we can provide a controller IP that supports DDR4, DDR3, DDR3L, LPDDR3, and LPDDR2 as a single IP solution.

Our DDR PHY IP family includes two families of DDR PHYs, high-speed (HS) PHYs and low-power (LP) PHYs, to address a range of applications for DDR. Delivery options include Firm IP and Hard IP, providing flexibility either to integrate a customized memory interface in your design, or to utilize a standard implementation to speed up integration on a wide range of technology nodes, including advanced nodes, such as 16nm FinFET.

DDR Resource Page

Click here for more information on our DDR4 16nm FinFET IP

Products

DDR ControllersFully configurable and customizable DDR controllers

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DDR Firm PHYConfigurable width DDR PHY's

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DDR Hard PHYFully hardened DDR PHY's

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Multi-Protocol DDR IPIntegrates a LPDDR4/3 DDR4/3 controller and a LPDDR4/3 DDR4/3 Firm PHY

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