Monitoring IP for SoC Designs | Cadence IP

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Monitoring IP

Cadence® Monitoring IP is a series of IP, derived from our ADC, and targeted to monitor the status of sections of a system on chip (SoC) or ASIC. This series of IP is used to report the voltage level, temperature, and process variation inside the SoC/ASIC to the CPU.

Our Monitoring IP is a critical component in applications such as dynamic voltage and frequency scaling (DVFS) for battery, power, or performance management. With a relatively small size and low power, these IP designs can be liberally placed across a large SoC/ASIC as needed. In newer nodes where process variation can vary significantly, Cadence Monitoring IP can assist in minimizing yield drops by compensating for voltage and process variation. 


  • High accuracy
  • Easy integration: low non-restrictive metal stacks and self-contained analog macro design
  • 12-bit digital readout