Home: IP Portfolio > Interface IP > USB IP

USB IP

Take the Shortest Path to Silicon Success

Cadence® USB IP solutions address the performance, power, and area requirements of today’s mobile, consumer, and enterprise (infrastructure) markets. Supporting both USB 2.0 and USB 3.0 specifications, Cadence provides a complete USB design IP solution with controller, PHY, software stack, verification IP, and an application platform to deliver the lowest risk path to SoC success.

Our open IP platform and IP Factory approach provide the configurability and customizability you need to streamline design, integration, and verification efforts, and minimize your software overhead. With Cadence USB IP, you can design with confidence, improve time-to-market, and lower die area with customized deliverables.

The vast majority of Cadence USB IP solutions are USB-IF certified, so you won’t have to worry about compliance or interoperability issues. Additionally, multiple hardware platforms are available for verification, validation, and certification. Select IPs are compliant with the TSMC Soft-IP 9000 program. 

Our USB 3.0 Controller IP includes the xHCI Host Controller and the Peripheral Device Controller. Cadence SuperSpeed USB 3.0 Controller IP is silicon proven and shipping in mass production. 

 

USB 3.0 xHCI Host Controller Supports all USB applications running in popular operating systems

The Cadence® USB 3.0 xHCI Host Controller IPprovides system-on-chip (SoC) designers with the most robust way to implement a USB interface in their applications. The IP is architected to quickly and easily integrate into any SoC as an integrated solution with any Cadence or third-party USB PHY IP. Host applications access the controller through the industry-standard ARM® AMBA® AXI system bus with an optional PCI Express (PCIe) interface. 

USB 3.0 xHCI

The Cadence USB 3.0 xHCI Host Controller IP implements an advanced, xHCI-based scatter-gather DMA interface to support all USB applications running in popular operating systems. Compliant with Universal Serial Bus 3.0 Specification, Revision 1.0 and xHCI Specification, Revision 1.0, the Cadence USB 3.0 xHCI Host Controller IPoperates in SuperSpeed (5Gbps), High-Speed (480Mbps), Full-Speed (12Mbps), and Low-Speed (1.5 Mbps) modes. The PHY interface complies with USB PHY Interface for PCI Express (PIPE) for USB 3.0, as well as USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, version 1.05.

Key Features

  • Compliant with USB 3.0 and xHCI specifications
  • SuperSpeed (5Gbps), High-Speed (480Mbps), Full-Speed (12Mbps), and Low Speed (1.5 Mbps) mode
  • Configurable number of USB 2.0 and USB 3.0 ports
  • Configurable number of supported devices
  • Up to 15 configurable IN and OUT endpoints per device
  • PIPE interface for USB 3.0 and UTMI for USB 2.0
  • AXI Master system bus interface with support for outstanding transactions
  • SSIC Interface option for MIPI M-PHY
  • Optional PCIe/M-PCIe system bus interface
  • Support for all USB Power management modes

Products

  • USB 3.0 Peripheral Controller IP

 

USB 3.0 Peripheral Controller Includes the SuperSpeed USB 3.0 Peripheral Device Controller

Cadence® USB 3.0 Controller IP is extensively tested, and fully compliant with the SuperSpeed USB 3.0 specification. Our USB 3.0 Peripheral Device Controller IP has been extensively validated in multiple hardware platforms and is now shipping in mass production through many customers. 

Cadence USB 3.0 Controller IP offers extensive configuration options for the best fit in your application. The IP is designed with the smallest silicon footprint and lowest power consumption in mind, so that it can satisfy the requirements of today’s mobile and consumer devices. The architectural flexibility of the USB 3.0 Controller IP enables both faster time-to-market as well as easy integration with all Cadence USB 3.0 PHY IP. 

The USB 3.0 Controller IP solution currently includes the Peripheral Device Controller.

SuperSpeed USB 3.0 Device Controller IP

 

Cadence SuperSpeed USB 3.0 Device Controller IP provides a SuperSpeed USB (5Gb/s) function interface that is certified by the USB Implementers Forum (USB-IF) to be compliant with the latest revision of the USB 3.0 specification. 

Our controller IP can be provided as a complete solution together with PHY, verification IP (VIP), software drivers, and customizable FPGA prototyping boards. 

A small silicon footprint, implementation of low-power modes, and support for all available USB classes make our SuperSpeed USB 3.0 Device Controller IP a perfect candidate for applications in mobile, consumer, and infrastructure markets. 

Cadence SuperSpeed USB 3.0 Device Controller IP is silicon-proven and shipping in mass production. 

Key Features

  • Certified by the USB-IF to be compatible with the final revision of the USB 3.0 specification
  • Configurable USB 3.0 PIPE interface (8-/16-/32-/64-bit)
  • High-/full-speed support with the UTMI/ULPI interface (optional)
  • Configurable 8-/16-/32-/64-bit OCP Slave/ARM® AMBA® AHB interfaces implemented as basic microprocessor interfaces
  • Integrated DMA controller with a configurable 32-/64-bit OCP Master/AMBA AHB interface
  • Control transfers supported by Endpoint 0
  • Up to 15 IN and 15 OUT configurable/programmable endpoints
  • Synchronous single-port RAM interface for endpoint buffers
  • Full-power management capabilities (U1, U2, and U3) with LFPS support
  • Supports bulk, interrupt, and isochronous transfers
  • Bulk stream support

Products

USB 3.0 Device IP USB 3.0 SuperSpeed Peripheral Device Controller IP                             

USB 3.0 PHY USB 3.0 PHY for device, hub, host, and OTG applications

Cadence® USB 3.0 Combo PHY IP is a hard PHY macro consisting of a USB 3.0 PHY core and a USB 2.0 PHY core. This IP is designed to the USB 3.0 v1.0 and USB 2.0 r2.0 specifications, and operates in SuperSpeed (5Gb/s), High-Speed (480Mb/s), and Full-Speed (12Mb/s) modes; Low-Speed mode is not supported. The USB 3.0 core complies with the PHY Interface for PCI Express® and USB 3.0 Architectures (v3.0) specifications, while the USB 2.0 core complies with the UTMI v1.05 specification.

Cadence USB 3.0 Combo PHY IP is architected to quickly and easily integrate into any system-on-a-chip (SoC) design, and to connect seamlessly to Cadence or third-party PIPE-compliant and UTMI-compliant controllers. Implemented on the TSMC 28HPM process, Cadence USB 3.0 Combo PHY IP provides a cost-effective, low-power solution for demanding applications. It offers SoC integrators advanced capabilities and support that exceed the requirements of high-performance designs and implementations.

Key Features

  • Compliant with USB 3.0 Specification Version 1.0, and USB 2.0 Specification
  • 8b/10b encoding/decoding implemented in hardware
  • USB 2.0 core for backward compatibility with UTMI interface; USB 3.0 PIPE interface
  • Supports 100MHz reference clock
  • Spread-spectrum clock/data recovery system and data scrambling to minimize EMI
  • Supports USB 2.0 and USB 3.0 applications
  • Low power, supports all USB 3.0 power management modes and includes extensive low-power features
  • Advanced testing features including DFT “stuck-at” test, flexible built-in self-test (BIST) circuit, and scan mode
  • Superior mixed-signal analog tools and techniques for high yield and margin for package and board variations
  • Loopback path after elastic buffer for USB 3.0 compliance loopback and BERT command test support

Products

USB 3.0 Combo PHY IP TSMC 28HPM                                  
USB 3.0 SuperSpeed PHY IP TSMC 28HPM

USB 2.0 Controller Family USB 2.0 HS Embedded Host, OTG, Device, Hub, and HSIC PHY Interface Controllers

Cadence® USB 2.0 Controller IP is silicon proven, and has been extensively validated with multiple hardware platforms. 

Every element of the USB 2.0 Controller IP provides a wide range of configuration options for the best fit in your SoC design. Small silicon footprint and low-power modes satisfy the requirements of today’s mobile and consumer devices. The flexible architecture of Cadence USB 2.0 Controller IP was developed with faster time-to-market in mind and can be easily integrated with our USB 2.0 PHY IP. 

Our USB 2.0 Controller IP includes the Embedded Host, On-The-Go (OTG), Device, and Hub Controllers. We also offer a USB 2.0 High-Speed Inter-Chip (HSIC) PHY Interface IP to facilitate connectivity between PHYs and Embedded Host and Device Controllers implemented in different chips on a single PCB.

USB 2.0 High-Speed Embedded Host Controller IP

Cadence® USB 2.0 High-Speed Embedded Host Controller intellectual property (IP) is a fully-functional host for devices specified in the Target Peripheral List (TPL), as defined in the USB 2.0 specification.

This IP connects seamlessly to a USB 2.0 PHY, enabling quick and easy integration into any system-on-chip (SoC) design.



Through the support for low-power modes defined in the USB specification, this IP can be implemented in a variety of battery-powered designs, such as smartphones or tablets.

Cadence USB 2.0 High-Speed Embedded Host Controller IP is silicon-proven and shipping in mass production.

Key Features

  • Complies with the USB 2.0 specification and the Embedded Host supplement to the USB 2.0 specification
  • TSMC® Soft-IP9000-compliant
  • A choice of store-and-forward or latency buffer architectures
  • Store-and-forward architecture features:
    • Supports one Low-, Full-, or High-Speed peripheral device in host mode
    • Configurable/programmable single, double, triple, or quad buffering
    • Optional scatter-gather, protocol-aware controller with a configurable 32-/64-bit OCP Master/ARM® AMBA® AHB interface
  • Latency buffer architecture characteristics:
    • Supports High-Speed hubs and multiple Low-, Full-, or High-Speed peripheral devices in host mode
    • Supports USB split transactions
    • Configurable/programmable TX FIFO size
    • Configurable/programmable RX FIFO size
    • Integrated multichannel DMA module with a 32-bit AMBA AHB master interface and a USB protocol-aware DMA engine
  • Support for Full-Speed and High-Speed data transfer in peripheral mode
  • Control transfers supported by Endpoint 0
  • Configurable for up to 15 IN and 15 OUT endpoints
  • Configurable/programmable number of endpoints
  • Configurable/programmable size of endpoints
  • Programmable type of endpoints (bulk, ISO, interrupt)
  • Variety of 8-/16-/32-bit CPU interfaces: AMBA AHB, PVCI, and others
  • A choice of PHY interfaces:
    • 8-/16-bit USB Transceiver Macrocell Interface (UTMI+ (Level3))
    • 8-bit UTMI+ Low Pin Interface (ULPI)
  • Suspend and resume power management functions
  • Synchronous Dual-Port RAM interface for endpoint buffers
  • Support for Link Power Management (LPM)
  • Remote Wake-Up function

Products

USB 2.0 High-Speed Embedded Host Controller IP Complies with the TPL in the USB 2.0 specification

USB 2.0 High-Speed OTG Controller IP

Cadence® USB 2.0 High-Speed On-the-Go (OTG) Controller intellectual property (IP) is a USB 2.0 dual-role device that meets the 2.0 revision of the USB specification and its On-the-Go supplement. Our USB 2.0 HS-OTG Controller provides functionality of embedded host and device controllers. 



Cadence USB 2.0 HS OTG Controller IP is provided with a complementary low-level driver and supports all USB classes defined in the specification, thus enabling quick and easy integration into any system on chip (SoC) design. The controller can also be integrated with any of the Cadence USB 2.0 PHY controllers.

Our USB 2.0 HS OTG Controller IP  is a silicon-proven design that is shipping in mass production.

Key Features

  • Complies with the USB 2.0 specification and the On-The-Go supplement to the USB 2.0 specification
  • TSMC® Soft-IP9000-compliant
  • Supports Host Negotiation Protocol, Session Request Protocol, and Attach Detection Protocol
  • A choice of store-and-forward or latency buffer architectures
  • Store-and-forward architecture features:
    • Supports one Low-,Full-, or High-Speed peripheral device in host mode
    • Configurable/programmable single, double, triple, or quad buffering
    • Optional scatter-gather, protocol-aware DMA controller with a configurable 32-/64-bit OCP Master/ARM®  AMBA® AHB interface
  • Latency buffer architecture characteristics:
    • Supports high-speed hubs and multiple low-, full-, or high-speed peripheral devices in host mode
    • Supports USB split transactions
    • Configurable/programmable TX FIFO size
    • Configurable/programmable RX FIFO size
    • Integrated multichannel DMA module with a 32-bit AMBA AHB master interface and a USB protocol-aware DMA engine
  • Support for Full-Speed and High-Speed data transfer in peripheral mode
  • Control transfers supported by Endpoint 0
  • Configurable for up to 15 IN and 15 OUT endpoints
  • Configurable/programmable number of endpoints
  • Configurable/programmable size of endpoints
  • Programmable type of endpoints (bulk, ISO, interrupt)
  • Variety of 8-/16-/32-bit CPU interfaces: AMBA AHB, PVCI, and others
  • A choice of PHY interfaces:
    • 8-/16-bit USB Transceiver Macrocell Interface (UTMI+ (Level3))
    • 8-bit UTMI+ Low Pin Interface (ULPI)
  • Suspend and resume power managements functions
  • Synchronous Dual-Port RAM interface for endpoint buffers
  • Support for Link Power Management (LPM)
  • Remote Wake-Up function

Products

USB 2.0 HS-OTG Controller IP Adds the On-The-Go supplement to USB 2.0

USB 2.0 High-Speed Device Controller IP

Cadence® USB 2.0 High-Speed Device Controller intellectual property (IP) provides a USB High-Speed and Full-Speed (480 and 12Mb/s) function interface that meets the 2.0 revision of the USB specification. 



Our USB 2.0 High-Speed Device Controller IP is available as an integrated solution with a choice of PHYs, verification IP (VIP), software stack, and customizable FPGA platform. 

This IP has been silicon-proven in numerous processes and configurations, and is available for implementation in any USB application, thanks to its support for all possible USB classes.

Key Features

  • Compliance with the USB 2.0 specification
  • Control transfers supported by Endpoint 0
  • Configurable for up to 15 IN and 15 OUT endpoints
  • Configurable/programmable number of endpoints
  • Configurable/programmable size of endpoints
  • Programmable type of endpoints (bulk, ISO, interrupt)
  • A choice of PHY interfaces:
    • 8-/16-bit USB Transceiver Macrocell Interface (UTMI)
    • 8-bit UTMI+ Low Pin Interface (ULPI)
  • Variety of 8-/16-/32-bit CPU interfaces: ARM® AMBA® AHB, PVCI
  • A choice of DMA controllers:
    • Protocol-aware controller with a 32-bit data bus and AMBA AHB/PVCI interfaces
    • Scatter-gather, protocol-aware controller with a configurable 32-/64-bit OCP Master/AMBA AHB interface
  • Synchronous RAM interface for endpoint FIFOs
  • Suspend and resume power management functions
  • Support for Link Power Management (LPM)
  • Remote Wake-Up function

Products

USB 2.0 High-Speed Device Controller IP Configurable for 480/12Mb/s interfaces

USB 2.0 High-Speed Hub Controller IP

Cadence® USB High-Speed 2.0 Hub Controller intellectual property (IP) is a configurable USB 2.0 hub controller that is compliant with the USB 2.0 specification and the USB 2.0 Link Power Management Addendum. 

 

This IP provides various interface options, with both a direct analog front end (AFE) and a PHY-integrated USB interface. Our USB 2.0 High-Speed Hub Controller IP can optionally support USB High-Speed Inter-Chip (HSIC) communication, with each port separately configurable to enable or disable this interface.

Apart from handling USB transactions, the group of main functional tasks performed by Cadence USB 2.0 High-Speed Hub Controller IP includes connectivity behavior, connect/disconnect detection, power management, bus fault detection, and recovery.

Our USB 2.0 High-Speed Hub Controller IP contains a Transaction Translator module that translates high-speed upstream port transactions to low-/full-speed downstream port transactions.

This IP has been designed for quick and easy integration into any system-on-a-chip (SoC) design, and for seamless connection to the USB 2.0 PHY.

Key Features

  • Complies with the USB 2.0 High-Speed specification and the Link Power Management addendum
  • Support for High-Speed, Full-Speed, and Low-Speed devices
  • 3 interface options:
    • Direct interface to the AFE
    • USB interface (with integrated PHY)
    • HSIC interface (optional)
  • Support for standard and hub specific requests
  • Single or multiple (optional) Transaction Translator for USB Low-/Full-Speed transfers
  • Up to 15 downstream ports
  • Each port can be configured to support USB HSIC PHY interface
  • Connect/disconnect detection of downstream ports
  • L0(On)/L1(Sleep)/L2(Suspend) power operating modes

Products

USB 2.0 High-Speed Hub Controller IP USB 2.0 Hub controller compliant with the USB 2.0 specification and USB 2.0 Link Power Management Addendum

USB 2.0 HSIC PHY Interface

Cadence® High-Speed Inter-Chip (HSIC) PHY intellectual property (IP) is a complete mixed-signal transceiver macro-cell that implements the USB 2.0 HSIC layer for USB 2.0 high-speed device and host applications. 



Our USB HSIC PHY IP consists of a logic macro, which is available as either hard or soft IP, and a hard IP block that contains the special driver circuit that is mandated by the HSIC specification. 

Our USB HSIC PHY IP can be used in any compact application where short-distance USB 2.0 connectivity is desired, but without the large die size and high power consumption of conventional USB 2.0 PHY IP.

Key Features

  • 8-bit (optionally 16-bit) parallel UTMI+ interface
  • Built-in self test (BIST)
  • Scan-based DFT
  • 1.2V ±10% driver supply

Products

USB 2.0 HSIC PHY Interface Controller Implements the USB 2.0 HSIC layer

USB 2.0 Full-Speed/Low-Speed Device Controller IP

Cadence® Full-Speed/Low-Speed Device Controller intellectual property (IP) meets the 2.0 revision of the USB specification. The controller can be configured to support either full-speed or low-speed data paths and enable transfer speeds of 12Mb/s or 1.5Mb/s, respectively. 

To facilitate implementation of our IP in your application, Cadence USB 2.0 Full-Speed Device Controller IP is delivered with a complementary low-level driver. Both the IP and the driver support all available USB 2.0 classes.

Key Features

  • Support for Full- or Low-Speed operation according to USB 2.0 specification
  • ARM® AMBA® AHB, OPB, or generic system bus interface
  • Up to 31 configurable endpoints
  • Automatic data retry mechanism
  • Data toggle synchronization mechanism
  • Suspend and resume power management functions
  • Remote Wake-Up function
  • Endpoint buffers Single-Port RAM interface
  • Optional DMA Engine

Products

USB 2.0 Full-Speed/Low-Speed Device Controller Configurable for 12Mb/s or 1.5Mb/s interfaces                                 

USB 2.0 OTG PHY USB 2.0 PHY for device, hub, host, and OTG applications

Cadence® USB 2.0 OTG PHY IP is a hard PHY macro consisting of a single USB 2.0 PHY core. This IP is designed to the USB 2.0 r2.0 specification, and operates at high speed (480Mb/s), full speed (12Mb/s), and low speed (1.5Mb/s). The USB 2.0 core complies with the UTMI v1.05 specification.

Cadence USB 2.0 OTG PHY IP is architected to quickly and easily integrate into any SoC, and to connect seamlessly to a Cadence or third-party UTMI-compliant controller. Implemented on the TSMC 28HPM and 28LP processes, Cadence USB 2.0 PHY IP provides a cost-effective, low-power solution for demanding applications. It offers SoC integrators the advanced capabilities and support that exceed the requirements of high-performance designs and implementations.

Cadence USB 2.0 OTG PHY IP is silicon proven, and has been extensively validated with multiple hardware platforms. 

Key Features

  • Compliant with USB 2.0, USB OTG, and USB 1.1 specifications
  • Supports 480Mb/s High-Speed (HS), 12Mb/s Full-Speed (FS), and 1.5Mb/s Low-Speed (LS) serial data transmission rates
  • External 12/24MHz reference clock input and 480MHz PLL output
  • Supports Battery Charge 1.2
  • Utilizes 8-bit/16-bit parallel UTMI interface to transmit and receive USB 2.0 cable data
  • SYNC/EOP generation and checking
  • Bit-stuffing and NRZI encoding
  • CDR and elastic buffer from serial stream on the USB
  • Single parallel data clock output (30MHz or 60MHz) to DC
  • Session Request Protocol (SRP)
  • Charge and discharge VBUS and detection
  • Host Negotiation Protocol (HNP)
  • Minimum 8mA output current on VBUS
  • Extensive low-power features including suspend mode
  • Built-in self test (BIST) and support for USB 2.0 test modes for electrical testing

Products

USB 2.0 OTG PHY TSMC 28LP
TSMC 28HPM