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PCI Express IP

IP for Supercomputing or Mobile Applications

Cadence® IP for PCI Express® (PCIe®) is a family of integrated, system-level IP solutions to address high-performance and low-power requirements for applications ranging from supercomputing platforms to storage solutions, server applications, and mobile platforms.  

Within the portfolio, you can choose the PCIe controller and PHY IP, or the Mobile PCIe (M-PCIe™) controller and M-PHY which bring PCIe capabilities to mobile applications.

Our open IP platform and highly configurable architecture allow you to configure and customize a controller to your specific needs through a web-based GUI. Our PCIe controller IP supports the latest PCI-SIG specifications, configurable from Gen1 x1 (2.5GT/s) to Gen3 x16 (128 GT/s), and available in root port, endpoint, and dual mode configurations. The controller area is optimized for each application to provide you with the best power and performance.

Our PCIe PHY IP supports Gen3, 2.1, and 1.1 operation with the Cadence controller for PCIe or any third-party PHY that supports a PIPE3 or PIPE4 interface.  

With Cadence, you can design with confidence, taking advantage of PCIe IP solutions complete with driver software including reference integration code for Linux.

Cadence is also an active member of the PCI-SIG® and a frequent presenter at DevCon events.

PCIe Resource Page

Learn more, visit our PCIe Resource Page.

PCI Express Controllers Comprehensive Gen1/Gen2/Gen3 solutions

Cadence® Controller IP for PCI Express® (PCIe®) addresses a broad range of high-performance as well as low-power requirements for a broad spectrum of applications, from supercomputing platforms to storage solutions, server applications, and mobile platforms.

Our PCIe controller IP, supporting the latest PCI-SIG® specifications, includes PCIe and M-PCIe™ controllers that provide unsurpassed flexibility with the ability to configure and customize a controller to your specific needs. The controller designs are highly configurable from Gen1 x1 (2.5GT/s) to Gen3 x16 (128GT/s), and are available in root port, endpoint, and dual mode configurations. The controller area is optimized for each application to provide you with the best power and performance.

Cadence PCIe controllers offer over 100 configurable features and 1,500 input parameters to optimize your design for the best area and performance for a specific application. Cadence controllers have been integrated with Cadence and third-party PHYs.

Key Features

  • AXI3 with optional DMA and Cadence hardware adaptation layer (HAL) interfaces
  • PIPE3 and PIPE4 support
  • Virtualization with SR-IOV and virtual function support
  • Controller bifurcation allowing a controller to function as two independent controllers
  • Support for latest ECNs, including all low-power ECNs (L1-substate, OBFF, Latency Tolerance Reporting, ASPM optionality)
  • Reliability, availability, and serviceability features
  • x1, x2, x4, x8, and x16 lane support

Deliverables

Cadence PCIe controller IP is delivered as clear, readable, synthesizable RTL with STA scripts, comprehensive user guides, and documentation. 

The PCIe product family also includes software drivers with reference integration code for Linux. You can accelerate software development on Cadence IP using our family of Virtual Reference Platforms.

Cadence has been a market leader in PCI controllers, and a significant number of x16 designs in silicon have been tested for interoperability and compatibility with a wide range of motherboards. Customers using our high-end designs have demonstrated performance that approaches the theoretical limits of throughput.

Cadence is an active member of the PCI-SIG and has presented at a number of DevCon events.

Products

Root Ports Gen1/2/3 with x1-x16 lane support
Endpoint Gen1/2/3 with x1-x16 lane support
Dual Mode Gen1/2/3 with x1-x16 lane support with the ability to strap the controller into root or end-point mode
Software Linux drivers                                 

PCI Express PHY PCIe Gen2/Gen3 and MIPI M-PHY solutions

Cadence® PHY IP for PCI Express® (PCIe®) addresses a broad range of high-performance as well as low-power requirements for a broad spectrum of applications, from supercomputing platforms to storage solutions, server applications, and mobile platforms.

Our PCIe PHY IP is silicon proven, and characterization reports and evaluation boards are available. PCIe PHY is built upon a robust and proven analog DFE-based architecture optimized for power. PHY performance exceeds the PCIe Gen3 requirements in jitter and long channel support. The PCIe PHY supports PCIe 3.0, 2.1, and 1.1 standard with PIPE 4.0 interface to the core. All the analog loops are completely adaptive, resulting in support for very short channel (chip-to-chip) to very long channel (backplane and board-to-board) applications.

The Cadence PHY IP for PCIe reduces time to production and time to bring-up with a rich set of built-in self test (BIST) and debug features. Advanced loop-back features, analog test bus, and support for on-chip oscilloscope enable you to adjust, observe, stress, and test the PHY functionality.

Key Features

  • x1, x2, x4, x8, and x16 lane support
  • Support for the latest ECNs, including all low-power ECNs:
    • L1-substate
    • Receiver termination
  • Multi-tap DFE for long channel support
  • On-chip regulation for improved jitter performance
  • PHY bifurcation, allowing a PHY to function as two independent PHYs
  • On-chip oscilloscope to obtain eye diagram and eye margining
  • BIST and loop-back support, pattern generation, and verification
  • Analog test bus

Deliverables

Cadence PHY IP for PCIe consists of the soft physical coding sub-layer (PCS) and the hard physical media attachment (PMA). Soft deliverables consist of synthesizable RTL with STA scripts. The hard portion consists of complete physical views. To ease SoC integration and package design, you can refer to comprehensive user guides and documentation. The design-in kit provides validation and flexibility for system design.

Products:

PCIe Gen3 PHY High-performance and low-power 3.0 PHY, 8Gbps with x1-x16 support
PCIe Gen2 PHY Low-power 2.1 PHY, 5Gbps with x1-x16 support
PCIe Gen1 PHY Low-power 1.1 PHY (2.5Gbps)
USB/PCIe PHY Low-power and area PHY (5Gbps), supports PCIe2/USB3
10G-KR/PCIe PHY Multi-protocol PHY supporting 10G-KR, PCIe3, XAUI, QSGMII, SGMII                                 

M-PCIe M-PCIe controller solution

Cadence® Controller IP for M-PCIe™ addresses a broad range of mobile applications, tapping into this latest addition to the PCIe® family. Target applications include application processors, wireless devices, and other components in the mobile ecosystem.

Our M-PCIe controller IP, supporting the latest PCI-SIG® specifications, provides unsurpassed flexibility with the ability to configure and customize a controller to your specific needs. The controller designs are highly configurable from High-Speed Gear1 x1 to High-Speed Gear3 x8, and are available in root port, endpoint, and dual mode configurations. The controller area is optimized for each application to provide you with the best power and performance.

Cadence M-PCIe controllers offer over 100 configurable features and 1,500 input parameters to optimize your design for the best area and performance for a specific application.

Key Features

  • AXI3 and Cadence hardware adaptation layer (HAL) interfaces
  • 10-, 20-, and 40-bit RMMI support
  • SR-IOV and virtualization
  • Support for asymmetric RX/TX lane combinations
  • x1, x2, x4, and x8 lane support

Deliverables

Cadence Controller IP for M-PCIe is delivered as clear, readable, synthesizable RTL with STA scripts, comprehensive user guides, and documentation. 

The M-PCIe product family also includes software drivers with reference integration code for Linux. You can accelerate software development on Cadence IP using our family of Virtual Reference Platforms.

Cadence has been a market leader in PCI controllers, with a significant number of designs in silicon that have been tested for interoperability and compatibility with a wide range of motherboards. Customers using our high-end designs have demonstrated performance that approaches the theoretical limits of throughput.

Cadence is a sponsor of the M-PCIe ECN as an active member of the PCI-SIG®, and we have presented at a number of DevCon events.

Products

Root Ports Gear1/Gear2/Gear3 support with x1-x8 lane combinations
Endpoint Gear1/Gear2/Gear3 support with x1-x8 lane combinations
Dual Mode Gear1/Gear2/Gear3 support with x1-x8 lane combinations and ability to strap the controller into root port or endpoint mode
Software Linux drivers                                 

M-PHY PCIe Gen2/Gen3 and MIPI M-PHY solutions

Cadence® M-PHY IP integrates a MIPI® M-PHY transmitter and receiver that support data rates up to 3,000Mbps per lane and a low-speed transceiver that supports both SYS and PWM modes. This IP is based on Version 1.4 of the MIPI M-PHY specification. The RMMI interface is integrated and interfaces with CSI-3, DigRFv4, LLI, SSIC, and UFS controllers. The implementation is modular and up to four lanes can be connected in parallel to increase the throughput.

Cadence provides you with a complete, single-vendor MIPI M-PHY application solution together with a proven MIPI DigRFV4 controller and others to help you improve time to market while reducing integration risk and cost. Cadence MIPI M-PHY IP provides a cost-effective, low-power display-interface solution for application processors and media processors for the mobile market.

Key Features

  • MIPI M-PHY TX/RX solution based on v1.4
  • M-PHY RMMI interface supports CSI-3, DigRFv4, LLI, SSIC, and UFS protocols
  • High-speed (HS) 3,000 Mbps data transfer per lane
  • Modular implementation with lane scalability up to four lanes
  • Supports both SYS and PWM mode at low-speed (LS) operation
  • Slew-rate control for EMI reduction
  • Supports terminated and non-terminated operation
  • Low-power dissipation and compact footprint
  • Power- and area-optimized lane configurations for CSI-3, DigRFv4, LLI, SSIC, and UFS protocols
  • Optimized and matched analog design resulting in low skew between lanes, maximizes timing margins
  • Compact and rectangular footprint when scaled to different lane configurations
  • Slew-rate control for EMI reduction
  • Integrated BIST capable of producing and checking PRBS, CRPAT, and CJTPAT

Products

MIPI M-PHY Available on multiple process nodes and in different configurations