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MIPI IP

Designing for Next-Gen Mobile Applications

Developing for mobile-focused applications brings intense pressure to keep pace with technology advances and differentiate SoC designs for competitive advantage.  Cadence provides an open IP platform with a fully configurable and application-optimized architecture, giving you more power to innovate your SoC designs. Choose from our broad portfolio of silicon-proven IP for MIPI® standards, including CSI-2 RX and TX, DSI-TX, DigRF, Slimbus, and M-PCIe controllers, all of which are compliant with MIPI Alliance specifications. We also offer complete silicon-proven D-PHY and M-PHY in many different process nodes.

Use our FPGA application board to test the controller along with PHY test-chip on a daughter card and have a high level of confidence in first-pass silicon. The board supports emulation as well as lab validation in a test-chip environment.

The Cadence® IP Factory approach ensures that our MIPI controller and PHY IP are delivered as verified and validated turnkey solutions, so you can pursue your design goals while accelerating time-to-market and reducing integration risk and cost.

    Resources

Products

MIPI DSI Transmitter DSI transmitter controller for application processor

Cadence® MIPI® DSI Transmitter (TX) IP is compliant with the MIPI Alliance DSI specification. This IP provides a high-speed serial interface between an application processor and a MIPI DSI-compliant display module. MIPI DSI TX Controller IP interfaces with the physical layer (MIPI D-PHY) through the MIPI-recommended PHY Protocol Interface (PPI). 

Cadence provides you with a complete, single-vendor MIPI DSI solution together with a proven MIPI D-PHY IP to help you improve time-to-market while reducing integration risk and cost. Cadence MIPI DSI Transmitter IP provides a cost-effective, low-power display interface solution for application processors and media processors for the mobile market.

MIPI CSI-2 Receiver CSI-2 receiver controller for application processor

Cadence® MIPI® CSI-2 Receiver (RX) IP is compliant with the MIPI Alliance CSI-2 specification. This IP provides a high-speed serial interface between an application processor and a MIPI CSI-2-compliant camera sensor. MIPI CSI-2 RX Controller IP interfaces with the physical layer (MIPI D-PHY) through the MIPI-recommended PHY Protocol Interface (PPI).

Cadence provides you with a complete, single-vendor MIPI CSI-2 solution together with a proven MIPI D-PHY IP to help you improve your time to market while reducing integration risk and cost. Cadence CSI-2 Receiver IP provides a cost-effective, low-power camera-interface solution for application processors and media processors for the mobile market. 

Key Features

  • CSI-2 v1.0 compliant
  • PPI
  • Bandwidth: 1 – 4 lanes. Each lane up to 1.5Gbps (DPHY v1.0)
  • Gate clocking for lower power operation
  • Low power, ULPS, optimized mode
  • Configuration interface: APB
  • Supports all preliminary and secondary video formats
  • Supports virtual channel management and data interleaving
  • ECC and CRC error detection
  • Built-in self test (BIST)

Products

CSI-2 RX Controller IP CSI-2 receiver controller for application processor 

MIPI CSI-2 Transmitter CSI-2 transmitter controller for application processor

Cadence® MIPI® CSI-2 Transmitter (TX) Controller IP is compliant with the MIPI Alliance CSI-2 Specification. This IP provides a high-speed serial interface between an application processor and a MIPI CSI-2-compliant camera sensor. MIPI CSI-2 TX Controller IP interfaces with the physical layer (MIPI D-PHY) through the MIPI-recommended PHY Protocol Interface (PPI).

Cadence provides you with a complete, single-vendor MIPI CSI-2 solution together with our proven MIPI D-PHY IP to help you improve your time to market while reducing integration risk and cost. Cadence MIPI CSI-2 IP provides a cost-effective, low-power camera-interface solution for application processors and media processors for the mobile market.

Key Features

  • CSI-2 v1.0 compliant
  • PPI
  • Bandwidth: 1 – 4 lanes, each lane up to 1.5Gbps (DPHY v1.0)
  • Gate clocking for lower power operation
  • Low power, ULPS, optimized mode
  • Configuration interface: APB
  • Supports all preliminary and secondary video formats
  • Supports virtual channel management and data interleaving
  • ECC error generation
  • Buit-in self test (BIST)

Products:

CSI-2 TX Controller IP   CSI-2 transmitter controller for application processor 

MIPI SLIMbus Controllers SLIMBUS device and manager controllers

Cadence® MIPI® SLIMbus IP helps achieve small size and high performance with its universal and mobile-optimized architecture. SLIMbus not only transfers audio data within an system-on-chip (SoC) design very efficiently, but it also supports transport of asynchronous data as well as control data. With its multi-drop architecture, MIPI SLIMbus triumphs over existing audio standards, like I2S or PCM, and eliminates the need for any control bus on audio components. The synchronous, 2-wire TDM frame structure and surrounding bus arbitration mechanisms and message structures establish flexible and robust data connections between various SLIMbus devices.

Cadence provides you with complete SLIMbus solutions in the device and manager sides. Our SLIMbus Device Controller IP is a MIPI-compliant SLIMbus Device controller. It implements Interface Device Class and Generic Device Class with up to 64 programmable data ports and, optionally, Framer Device Class. Our SLIMbus Manager Controller IP is a MIPI-compliant SLIMbus Manager controller that implements Interface Device Class, Manager Device Class and, optionally, Framer Device Class and Generic Device Class.

Products

MIPI SLIMbus Device Controller

Cadence SLIMBUS Device Controller IP is a MIPI-compliant SLIMbus device controller. It implements Interface Device Class, Generic Device Class with up to 64 programmable data ports and, optionally, Framer Device Class. Our SLIMbus-DEV is a highly configurable product of scalable architecture that enables seamless adoption by any user application. Full compliance with the MIPI SLIMbus specification enables users to enjoy all of the benefits of the SLIMbus standard, including dynamic bus reconfiguration, multiple simultaneous independent data transmissions, and power consumption optimization. 

Key Features

  • Compliant with MIPI SLIMbus version 1.02
  • Full support for all SLIMbus Core messages, including bus reconfiguration, channel allocation, and Value and Information messages
  • Support for all Core, Interface, Framer Device, and Generic Device Information elements
  • Automatic transmission of reply and report messages
  • AHB interface for communication with the CPU
  • RX and TX FIFOs, with configurable sizes, for received and transmitted messages
  • Sniffing function that allows storage of all messages detected on the bus
  • Data Ports (generic interface that uses parallel data and handshake synchronization) for data communication
  • Control Port for control communication
  • Extensive configurability options that can be set by either parameters, pin strapping, or register settings

MIPI SLIMbus Manager Controller

Cadence SLIMbus Manager Controller IP implements Interface Device Class, Manager Device Class, and, optionally, Framer Device Class and Generic Device Class. This component has a highly configurable and scalable modular architecture that enables seamless adoption by any user application—from simple devices through audio processors to advanced mobile chipsets. It supports most advanced MIPI SLIMbus features, which include dynamic bus reconfiguration and power consumption optimization. Thanks to programmable Sniffing and Active Manager functions, the component may operate as Active Manager, SLIMbus message traffic monitor, or both.

Key Features

  • Compliant with MIPI SLIMbus specification version 1.02
  • Full support for all SLIMbus Core messages, including bus reconfiguration, channel allocation, and Value and Information messages
  • Support for all Core, Interface, Framer Device, and Generic Device Information Elements
  • Automatic transmission of reply and report messages
  • AHB interface for communication with CPU
  • RX and TX FIFOs, with configurable sizes, for received and transmitted messages
  • Sniffing function that allows storage of all messages detected on the bus
  • Data Ports (generic interface that uses parallel data and handshake synchronization) for data communication
  • Control Port for control communication
  • Extensive configurability options that can be set by either parameters, pin strapping, or register settings

MIPI DigRF V4 Controller Master and slave controller for DIGRF V4

Cadence® MIPI® M-PHY IP is compliant with the MIPI Alliance Specification for DigRF v4 version 1.10 (now referred to as the MIPI DigRF v4 standard). It supports a single-link solution with up to four lanes for RxData Sublink and up to two lanes for TxData Sublink. The solution can also be configured as two links of up to two lanes for RxData Sublink and one lane for TxData Sublink during remote diversity application. This IP provides solutions for both master (BBIC) and slave (RFIC) controllers.

Cadence provides you with a complete, single-vendor MIPI DigRF V4.0 solution together with a proven MIPI M-PHY to help you improve your time to market while reducing integration risk and cost. Cadence MIPI DigRF V4.0 Controller IP provides a cost-effective, low-power MIPI M-PHY solution for application processors and media processors for the mobile market.

Key Features

  • Master and slave controllers for MIPI DigRF v4 interface
  • Compliant with MIPI Alliance Specification for DigRF v4 version 1.10
  • Supports LTE, Mobile WiMax, dual mode 3GPP such as 2.5G/3.5G
  • Remote diversity solution with two links of up to two lanes for RxData Sublink and one lane for TxData Sublink
  • Single-link solution with up to four lanes for RxData Sublink and up to two lanes for TxData Sublink
  • DATA/CTRL SAP (Only 1X symbols width)
  • Supports four parallel data logical channels per SubLink
  • Supports low-speed (LS), high-speed 1X primary (HS1P), high-speed 1X secondary (HS1S), high-speed 2X primary (HS2P), and high-speed 2X secondary (HS2S) modes
  • Common reference RefClk to BBIC and RFIC (10-100MHz for LS mode, 19.2/26/38.4/52MHz for HS mode)
  • Link optimized to reduce power by switching between active and low-power mode
  • Sleep, stall, hibernate, and shutdown modes to reduce power
  • Multiple error detection and correction schemes
  • Supports for link test modes: ping test, clock test mode, line loopback mode, and logic loopback mode

Products

DIGRF-V4 Controller IP Master and slave controller for DIGRF V4                                 

MIPI BIF Master Controller Battery interface controller

Cadence® MIPI® BIF Master Controller IP is compliant with battery interface (BIF) v1.0. MIPI BIF defines a low-level communication protocol and establishes a digital data link between the battery (the BIF slave) and a device using the battery (the BIF master). Cadence provides the MIPI BIF master controller for devices using the BIF interface to communicate with BIF-supported batteries. 

Key Features

  • Open drain (and push-pull support)
  • Hardware master protocol interface
  • Software bus transaction layer abstraction for function, commands
  • Broadcast bit, 10-bit data packet, 4-bit parity, inversion bit
  • Time distance coding
  • Parity error and CRC checking
  • Single slave or broadcast commands
  • APB 8-bit data interface
  • Single event interrupt
  • Timeout control

Products

BIF Controller IP Battery interface controller

MIPI D-PHY D-PHY physical layer

Cadence® MIPI® D-PHY IP integrates a MIPI high-speed transmitter and receiver that support data rates up to 1.5Gbps per lane, and a MIPI low-power transceiver that enables bidirectional data transfer. This IP is based on Version 1.1 of the MIPI D-PHY spec. The digital D-PHY is integrated and interfaces with controllers of MIPI CSI2 and DSI protocols. The architecture supports connection of multiple data lanes in parallel. Up to four data lanes can be connected to increase the total throughput to 6Gbps.

Cadence provides you with a complete, single-vendor MIPI CSI-2 and DSI solution together with our proven MIPI CSI-2 controller and DSI controller to help you improve your time to market while reducing integration risk and cost. Cadence MIPI D-PHY IP provides a cost-effective, low-power MIPI D-PHY solution for application processors and media processors for the mobile market.

Key Features

  • MIPI D-PHY TX/RX solution based on v1.1 specification
  • PPI supporting CSI2 and DSI MIPI  protocols
  • High-speed 1.5Gbps data transfer per lane; low-power 10Mbps data transfer
  • Lane scalability up to four providing  6Gbps transfer rate
  • ULPS and Contention Detection mode
  • Uni- and bi-directional lane modes
  • Automatic termination control for high-speed and low-power modes
  • Low-power dissipation; compact and rectangular footprint even when scaled to different lane configurations
  • Optimized and matched analog design resulting in low clock-data lane skew
  • Maximization of timing margins due to low skew between data and clock lanes
  • Automatic termination control for high-speed and low-power modes
  • Built-in sequence error detection for receiver
  • Integrated BIST capable of producing and checking PRBS, CRPAT, CJTPAT

 Products

MIPI D-PHY is available on multiple process nodes and in different configurations

MIPI M-PHY M-PHY physical layer

Cadence® M-PHY IP integrates a MIPI® M-PHY transmitter and receiver that support data rates up to 5.8Gbps per lane and a low-speed transceiver that supports both SYS and PWM modes. This IP is based on Version 3.0 of the MIPI M-PHY specification. The RMMI interface is integrated and interfaces with CSI-3, DigRFv4, LLI, SSIC, and UFS controllers. The implementation is modular and up to four lanes can be connected in parallel to increase the throughput.

Cadence MIPI PHY solutions have passed silicon validation in different process nodes. Take advantage of flexible options to evaluate your chosen PHY solution: PHY electrical characteristics validated through test-chip vehicles/PVT char, PHY suitability for applications validated through controller emulation on FPGA with PHY on daughter card, and customer emulation of MIPI applications using Cadence MIPI PHY daughter cards (with both Cadence and third-party controllers).

Cadence provides you with a complete, single-vendor MIPI M-PHY application solution together with our proven MIPI DigRFV4 controller and others to help you improve your time to market while reducing integration risk and cost. Cadence MIPI M-PHY IP provides a cost-effective, low-power display interface solution for application processors and media processors for the mobile market.

Key Features

  • MIPI M-PHY TX/RX solution based on v3.0
  • M-PHY RMMI interface supports CSI-3, DigRFv4, LLI, SSIC, and UFS protocols
  • High-speed 5.8Gbps data transfer per lane
  • Modular implementation with lane scalability up to four lanes
  • Supports both SYS- and PWM-mode low-speed operation
  • Slew-rate control for EMI reduction
  • Supports terminated and non-terminated operation
  • Low-power dissipation and compact footprint
  • Power- and area-optimized lane configurations for CSI-3, DigRFv4, LLI, SSIC, and UFS protocols
  • Optimized and matched analog design resulting in low skew between lanes, maximizes timing margins
  • Compact and rectangular footprint when scaled to different lane configurations
  • Slew-rate control for EMI reduction
  • Integrated built-in self test (BIST) capable of producing and checking PRBS, CRPAT, and CJTPAT

Products

MIPI M-PHY Available on multiple process nodes and in different configurations

MIPI UniPro Controller UniPro V1.6 Controller

As part of the Cadence IP factory, the Cadence Unipro v1.6 controller—together with the Cadence M-PHY—builds a complete Unipro solution that fully supports the UFS2.0, CSI-3 standard as well as many applications using Unipro v1.6 to build up the application network.  

The Cadence MIPI Unipro IP is fully compliant with the MIPI Alliance Specification for Unipro version 1.6. It supports the MIPI Alliance Specification for CSI-3 version 1.0 and the JEDEC® specification for UFS version 2.0.

The Cadence MIPI Unipro IP is a versatile design supporting multiple lanes and multiple gears to enable a diverse range of UFS and CSI-3 applications. The Cadence MIPI Unipro IP is architected to a fast and seamless integration into any SoC on application-layer level and to a Cadence or third-party RMMI-compliant M-PHY module on the physical-layer level. The Cadence MIPI Unipro IP provides a highly configurable, cost-effective, low-power solution for demanding applications. It offers SoC integrators advanced capabilities that do not only meet, but exceed the requirements of high-performance designs and implementations.

Key Features

  • Compliance with MIPI Unipro v1.6, MPHY v3.0
  • Internal CPort arbitration
  • Multi-gear, multi-lane, high-speed, and PWM support
  • End-to-end flow control
  • Automatic retransmission on erroneous reception
  • Skip symbol insertion/deletion to handle clock offsets
  • Support for two traffic classes—TC0 and TC1
  • Scrambler function to reduce EMI
  • Frame prioritization through pre-emption
  • Optional integrated solution with Cadence M-PHY
  • Configurable number of CPorts
  • ARM® AMBA® APB interface for DME

Products

MIPI UniPro MIPI UniPro v1.6 Controller

MiPI SoundWire Controller Audio data transport and control

The Cadence® MIPI® SoundWire Controller IP is designed according to the MIPI SoundWire standard and provides low-cost, low-power connectivity for audio data transport and control. MIPI SoundWire interface  provides two representative types of connectivity. The first type carries PCM audio data between a mobile application processor and a standalone audio codec or Bluetooth/FM radio controller. The second type carries PDM audio data between the audio codec and MEMS microphone or speaker amplifiers.

The Cadence MIPI SoundWire Controller IP uses a modular and layered design approach. Configurable parameters are provided to customize client interface, FIFO width/depth, port count, lane count, clocking scheme etc. for area and power optimized solution. 

Products

MIPI SoundWire Master Controller

MIPI SoundWire 2

The Cadence MIPI SoundWire Master Controller IP is compliant with MIPI Soundwire Standard and uses a modular and layered design approach. Configurable parameters are provided to customize client interface, FIFO width/depth, port count, lane count, clocking scheme etc. for area and power optimized solution. 

Key Features

  • Standard-based master IP with multi-lane capability
  • AHB-based software control
  • Bi-directional or uni-directional FIFO-based physical data ports for low latency audio streaming
  • Configurable data port count, port width, port FIFO sizes
  • Multi-entry command FIFO for READ/WRITE/PING commands, accessible through AHB interface or direct FIFO interface
  • Automatic PING generation
  • Bus command ownership BREQ/BREL handshake
  • Flexible frame structure
  • Static and dynamic frame sync generation
  • Frame parity generation and parity error detection
  • Slave status and data transfer status interrupts
  • Isochronous, Tx-controlled, Rx-controlled or asynchronous transport
  • Bulk transport protocol support
  • Multi-lane and multi-master stream synchronization
  • Synchronized bank switching to adjust frame parameters and sample rate
  • Static-1, static-0, PRBS test pattern generation
  • Loopback modes
  • Flexible clock generation based on clock gear box
  • ClockStop support with asynchronous self- or device- wakeup

 

MIPI SoundWire Slave Controller

Key Features

 

Deliverables

  • Lint-clean, configurable, synthesizable Verilog RTL
  • Synthesis and STA scripts
  • Documentation – integration and user guide, release notes
  • Sample verification testbench with integrated BFM and monitors