Timing IP for SoC Designs | Cadence IP

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Timing IP

Cadence® Timing IP is a series of hardened IP, silicon-proven at leading-edge nodes, that includes phase-locked loops (PLLs) and oscillators to address the timing requirements of a typical system-on-chip (SoC) silicon. Our Timing IP is ideal for applications where capture range and clock performance are critical.

It is designed for easy integration with any SoC design by utilizing low, non-restrictive metal stacks. The IP is designed to minimize changes in circuit performance in applications where jitter, capture range, and clock performance are critical. Cadence Timing IP is a companion to our ADC IP and DAC IP to create custom analog front ends (AFEs) for your specific applications. It is also used to integrate with our line of Interface IP. 


  • Internal regulator for supplynoise tolerance
  • Easy integration: Low non-restrictive metal stacks and self-contained analog macro design

Key Features

  • Input freq < 32KHz, Output frequency up to 5Ghz
  • Available for process nodes from 65nm to 16/14nm