ADC IP for SoC Designs | Cadence IP

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Cadence® ADC IP is a set of hardened IP for converting analog signals to digital data. Cadence ADC IP comes in single-, dual-, and octal-channel versions with resolutions up to 12 bits, conversion rates up to 3.5Gsps, and compact single ADC sizes (<0.1mm^2).

We are one of the earliest advocates of successive approximation register (SAR) ADC architecture. Today, we have more than 25 years of design experience, and our ADC includes unique and patented features for a high-performance, low-power, reliable, and compact-size ADC.

IP can be configured for:

  • Process nodes from 65nm to 16/14nm
  • High speed ADC (> 250Msps)
  • Medium speed ADC (100-250Msps)
  • Low speed ADC (<100Msps)


  • Silicon-proven solution for leading-edge nodes
  • Easy integration: low non-restrictive metal stacks and self-contained analog macro design
  • High performance > 10 ENOB for up to 12 bits ADC