Emulation Strategies

Customers can deploy a variety of strategies for emulation of Cadence® Tensilica®-based SoC designs.

  • Some SoC designers use the RTL source code produced by the Tensilica Xtensa® Processor Generator, or the pre-optimized Xilinx NGO files automatically producted by the Xtensa Processor Generator, to support FPGA-based boards of their own design as part of a comprehensive SoC methodology.
  • Other customers use commercial emulation systems in their SoC design process. The Tensilica processors work with all popular commercial emulation systems.
  • For standalone Xtensa processor emulation for upper-level code porting and development on Xtensa-based designs, designers can use the Virtex-6 FPGA ML605 Xilinx-based development kit.

Hardware/Software Co-Verification

Cadence's Tensilica processors work seamlessly with Cadence's system design and verification flow. Offering higher throughput, superior hardware/software debug, and fast compilation, the Cadence System Development Suite allows software developers to run and debug their designs on top of a set of open, connected, and scalable platforms. The suite includes the Cadence Palladium® XP hardware/software verification computing platform, which lets designers rapidly emulate a system-level design envirionment.  Be sure to visit the Cadence website to find out more.